1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of Related Art
In semiconductor devices such as a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor), a gate lead-out electrode for leading out a gate electrode of a MOSFET cell, so-called a gate finger is disposed to the outer periphery of a cell region where a number of MOSFET cells are arranged.
Japanese Unexamined Patent Application Publication (JP-A) No. 9-139496 (Reference 1) describes a cell region in which plural MOSFET cells 10 each having an N−type epitaxial layer 2 that functions as a drain formed on an N-semiconductor substrate 1, a P-type well 3 and a ring-like rectangular N+ type source region 4 formed in the surface layer portion thereof and a gate electrode 6 formed via a gate oxide film 5 above the substrate so as to ride over an MOSFET cell 10 arranged in a matrix as a vertical MOSFET (refer to FIG. 6A and FIG. 6B).
As shown in FIG. 6B, a source electrode 8 made of aluminum for connecting the source regions 4 of each of the MOSFET cells 10 is formed on the surface of the chip, and the source electrode 8 is connected with a source pad 11.
Further, as shown in FIG. 6A, a gate finger 13 is disposed about at the outer periphery of the cell region.
Further, the gate finger 13 is disposed on the gate oxide film 5 formed above the surface of the semiconductor substrate 1, composed of a polysilicon layer 6a for leading out a gate formed indivisibly with the gate electrode 6 made of polysilicon and an aluminum layer 13a disposed thereon, and is connected to a gate pad 12.
Further, the gate electrode 6 and the polysilicon layer 6a are covered with an interlayer insulation film 7 so as not to short circuit with the source electrode 8. Further, a drain electrode 9 made of aluminum is formed on the rear face of the semiconductor substrate 1.
On the other hand, Japanese Unexamined Patent Application Publication (JP-A) No. 2001-36081 (Reference 2) describes a constitution in which gate signal wirings made of aluminum extending in the direction where plural gate electrode portions are arranged by way of an interlayer insulation film above a polysilicon wirings of a DMOSFET formed in a ladder-shape, and the gate signal wirings thereof are electrically connected with the polysilicon wirings through plural contact vias (refer to FIG. 8A and FIG. 8B).
As shown in FIG. 8A, a wiring pattern portion 21 is connected to the gate signal wirings 25 of the upper layer made of aluminum through plural contact vias 29 formed in a first interlayer insulation film (not illustrated). Further, the gate signal wiring 25 has a pad portion 25a and an extension portion 25b extending from the pad portion 25a along a gate connection wiring portion 24. As shown in FIG. 8B, the gate signal wiring 25 is covered with a second interlayer insulation film (not illustrated). A source lead-out wiring 26 and a drain lead-out wiring 27 of the upper layer made of aluminum are formed over the second interlayer insulation film.
Further, reference 2 describes that an interlayer connection pad (not illustrated) is formed in the same layer with a gate signal wiring 25 for electrically connecting a source lead-out wiring 26 and a drain lead-out wiring 27 with a source region 22 and a drain region 23, respectively.
However, the present inventor considers that the prior art described above involves the following problems and a further improvement is necessary therefor. The problems in the technique described for FIG. 6A and FIG. 6B to be described with reference to
FIG. 7. FIG. 7 is a plan view schematically showing a flow of an electric current of the semiconductor device shown in FIG. 6A and FIG. 6B.
In the vertical power MOSFET described above, current flows to a source electrode 8 as shown in FIG. 7. In this case, since the source electrode 8 and a gate finger 13 are formed in a common layer, it is necessary that the source electrode 8 is arranged so as not to overlap the gate finger 13. Since the gate finger 13 is arranged in a state of intruding into the cell region so as to traverse the cell region, the current branches into a current Iinside flowing in the source electrode 8 inside of the gate finger 13 and a current Ioutside flowing in the outside source electrode 8 of the gate finger 13. As shown in FIG. 7, since the current Ioutside has to flow through a path round about the gate finger 13 and the current path is made longer by so much when compared with the current Iinside. As a result, this increases the entire on-resistance of the vertical power MOSFET.
On the other hand, in the technique described for FIG. 8A and FIG. 8B, since the source lead-out wiring 26 (source electrode) and the gate signal wiring (gate finger) 25 are formed in different layers, pattern layout for each of them can be designed flexibly. However, this involves a problem that the number of steps of forming the interlayer insulation film increases more compared with the semiconductor device shown in FIG. 6A and FIG. 6B. That is, when the gate signal wiring 25 made of aluminum is patterned, it is necessary to form an interlayer insulation film for protecting the polysilicon wiring in the lower layer and an interlayer insulation film for insulating the gate signal wiring 25 and the source lead-out wiring 26. Further, increase in the number of the layers for the interlayer insulation film is not preferred since this increases the chip thickness and may possibly increase the frequency for the occurrence of cracking or peeling in the interlayer insulation film.